DDR4 Memory Interface on Speedster7t FPGA | Achronix Demo

See a demonstration of a Speedster7t FPGA reading and writing to DDR4 memory components on the VectorPath™ Accelerator Card. This demonstration shows how to configure the interface using ACE design tools, program the FPGA, train the memory link, then issue 8,000 write and read transactions to verify the data. This design uses the Speedster7t 2D network on chip or NoC to route the data from the FPGA fabric to memory interface without a single line of RTL code for this part of the design. The VectorPath® S7t-VG6 accelerator card is designed to reduce time to market when developing high-performance compute and acceleration functions for artificial intelligence (AI), machine learning (ML), networking and data center applications. The card features Achronix’s high-performance Speedster7t AC7t1500 FPGA fabricated on TSMC's 7nm FinFET technology. Explore Speedster7t FPGAs: https://www.achronix.com/product/speedster7t-fpgas Speedster®7t FPGAs are optimized for high-bandwidth workloads and eliminate the performance bottlenecks associated with traditional FPGAs. Achronix and BittWare launched the VectorPath Accelerator Card with Speedster7t FPGAs in 2019. Get started with Achronix today: https://www.achronix.com/welcome_to_achronix

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